Semiconductor memory devices employ an array of memory cells arranged in columns and rows to cover an area of an integrated circuit (IC) chip. The cells are addressed by means of decoder circuitry that select the cell to be addressed and its memory content read out by way of a sense amplifier. When an array is made very large, the stray capacitance of the circuits becomes large. When a voltage responsive sense amplifier arrangement is employed, a large array entails the charging and discharging of a relatively large shunt capacitance and the speed of response is slowed. However, if the sense amplifier is made responsive to the memory array current, and the voltage swings reduced to a small value, the large capacitance of a large array does not limit the speed of response. Accordingly, it is desirable to employ reduced voltage swing current sensing amplifiers. In particular, a differential current sense amplifier is desired in which a reference current is compared with the memory current and an output voltage generated to indicate the comparison.